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| February 2005 rev 1.5 ASM1832 3.3V P Power Supply Monitor and Reset Circuit Devices are available in 8-pin PDIP, 8-pin SO and compact 8pin MicroSO packages. General Description The ASM1832 is a fully integrated microprocessor supervisor. It can halt and restart a "hung-up" microprocessor, restart a microprocessor after a power failure. It has a watchdog timer and external reset override. RESET and RESET outputs are push-pull. A precision temperature-compensated reference and Key Features * * * * * * * * * * * 3.3V supply monitor Push-pull output Selectable watchdog period Debounce manual push-button reset input Precision temperature-compensated voltage reference and comparator. Power-up, power-down and brown out detection 250ms minimum reset time Active LOW and HIGH reset signal Selectable trip point tolerance: 10% or 20% Low-cost 8-pin DIP/SO and 8-pin Micro SO packages Wide operating temperature -40C to +85C comparator circuits monitor the 3.3V, VCC input voltage status. During power-up or when the VCC power supply falls outside selectable tolerance limits, both RESET and RESET become active. When VCC rises above the threshold voltage, the reset signals remain active for an additional 250ms minimum, allowing the power supply and system microprocessor to stabilize. The trip point tolerance signal, TOL, selects the trip level tolerance to be either 10% or 20%. A debounced manual reset input, PBRST, activates the reset outputs for a minimum period of 250ms. There is a watchdog timer to stop and restart a microprocessor that is "hung-up". The watchdog timeouts periods are selectable: 150ms, 610ms, and 1200ms. If the ST input is not strobed LOW before the time-out period expires, a reset is generated. Applications * * * * * Microprocessor systems Computers Controllers Portable instruments Automotive systems Typical Operating Circuit 3.3V Block Diagram ASM1832 Tolerance Selection + VCC 40K PBRST Push Button Debounce Voltage Sense Comparator Watchdog Transition Detector Reset & Watchdog Timer RESET Reference VCC VCC VCC ASM1832 ST I/O P TOL RESET - RESET GND TD TOL RESET TD ST GND Alliance Semiconductor 2575 Augustine Drive . Santa Clara, CA 95054 . Tel: 408.855.4900 . Fax: 408.855.4999 . www.alsc.com Notice: The information in this document is subject to change without notice February 2005 rev 1.5 ASM1832 Pin Configuration PBRST TD TOL GND 1 2 3 4 8 VCC ST RESET RESET ASM1832 7 6 5 Pin Description Pin # 8-Pin Package 1 2 Pin Name PBRST TD Function Debounced manual pushbutton reset input. Watchdog time delay selection. (tTD = 150ms for TD = GND, tTD = 610ms for TD=Open, and tTD = 1200ms for TD = VCC). Selects 10% (TOL connected to GND) or 20% (TOL connected to VCC) trip point tolerance. Ground. Active HIGH reset output. RESET is active: 1. If VCC falls below the reset voltage trip point. 3 4 TOL GND 5 RESET 2. If PBRST is LOW. 3. If ST is not strobed LOW before the timeout period set by TD expires. 4. During power-up. Active LOW reset output. (See RESET). Strobe input. 3.3V power. 6 7 8 RESET ST VCC 3.3V P Power Supply Monitor and Reset Circuit Notice: The information in this document is subject to change without notice 2 of 9 February 2005 rev 1.5 ASM1832 . the microprocessor or Tolerance Select TOL = VCC TOL = GND Tolerance TRIP Point Voltage (V) Min 20% 10% 2.47 2.80 Nom 2.55 2.88 Max 2.64 2.97 Detailed Description The ASM1832 monitors microcontroller power supply and issues reset signals, both active HIGH and active LOW, that halt processor operation whenever the power supply voltage levels are outside a predetermined tolerance. RESET and RESET outputs RESET and RESET signals are active for a minimum of 250ms after the supply has returned to in-tolerance level. This allows the power supply and monitored processor to stabilize before instruction execution is allowed to begin. Trip Point Tolerance Selection The TOL input is used to determine the level VCC can vary below 3.3V without asserting a reset. With TOL conected to VCC, RESET and RESET become active whenever VCC falls below 2.64V. RESET and RESET become active when the VCC falls below 2.98V if TOL is connected to ground. After VCC has risen above the trip point set by TOL, RESET and RESET remain active for a minimum time period of 250ms. On power-down, once VCC falls below the reset threshold RESET stays LOW and is guaranteed to be 0.4V or less until VCC drops below 1.2V. The reset output on the ASM1832 uses a push-pull drive stage that can maintain a valid output below 1.2V. To sink current with VCC below 1.2V, a resistor can be connected from the reset pin (RESET) to Ground. This configuration will give a valid value on the reset output with VCC approaching 0V. During both power up and down, the configuration will draw current when the RESET is in the high state. The value of 100K should be adequate to maintain a valid condition. The active HIGH reset signal is valid down to a VCC level of 1.2V also. tR VCCTP(MAX) VCCTP tRPU VCC VOH RESET VCCTP(MIN) ~ ~ ~ ~ Figure 1: Timing Diagram : Power Up VOL RESET ~ ~ VCC VCCTP (MAX) VCCTP VCCTP (MIN) tF RESET tRPD VOH VOL ~~ ~~ RESET Figure 2: Timing Diagram : Power Down ASM1832 RESET 100k Microprocessor RESET Application Information Manual Reset Operation Push-button switch input, PBRST, allows the user to override the internal trip point detection circuits and issue reset ~ 3.3V P Power Supply Monitor and Reset Circuit Notice: The information in this document is subject to change without notice 3 of 9 February 2005 rev 1.5 signals. The pushbutton input is debounced and is pulled HIGH through an internal 40k resistor. When PBRST is held LOW for the minimum time tPB, both resets become active and remain active for a minimum time period of 250ms after PBRST returns HIGH. ASM1832 minimum timeout period, reset signals become active. On power-up after the supply voltage returns to an in-tolerance condition, the reset signal remains active for 250ms minimum, allowing the power supply and system microprocessor to stabilize. ST Pulses as short as 20ns can be detected. The debounced input is guaranteed to recognize pulses greater than 20ms. No external pull-up resistor is required, since PBRST is pulled HIGH by an internal 40k resistor. The PBRST can be driven from a TTL or CMOS logic line or shorted to ground with a mechanical switch. RESET ST Valid Strobe Valid Strobe Invalid Strobe tST tRST tTD (min) tTD (max) ~ ~ PBRST tPDLY VIL tPB VIH Note: ST is ignored whenever a reset is active Figure 5: Timing Diagram: Strobe Input Timeouts periods of approximately 150ms, 610ms or 1,200ms are selected through the TD pin. ~ ~ tRST RESET RESET TD Voltage level VOH VOL Watchdog Time-out Period (ms) Min Nom 150 610 1200 Max 250 1000 2000 Figure 3: Timing Diagram: Pushbutton Reset ~~ ~~ Supply Voltage ASM1832 1 2 3 4 PBRST TD TOL GND VCC 8 ST RESET RESET GND Floating VCC 62.5 250 500 The watchdog timer can not be disabled. It must be strobed with a high-to-low transition to avoid watchdog timeout and I/O 7 6 5 reset. P Supply Voltage ASM1832 1 2 3 4 PBRST TD TOL GND VCC 8 ST RESET RESET MREQ RESET Figure 4: Application Circuit: Pushbutton Reset 7 6 5 P RESET Address Bus Watchdog Timer and ST Input A watchdog timer stops and restarts a microprocessor that is "hung-up". The P must toggle the ST input within a set period (as selectable through TD input) to verify proper software execution. If the ST is not toggled low within the Decoder Figure 6: Application Circuit: Watchdog Timer 3.3V P Power Supply Monitor and Reset Circuit Notice: The information in this document is subject to change without notice 4 of 9 February 2005 rev 1.5 ASM1832 Absolute Maximum Ratings Parameter Voltage on VCC Voltage on ST, TD Voltage on PBRST, RESET, RESET Operating Temperature Range Soldering Temperature (for 10 sec) Storage Temperature ESD rating HBM MM Min -0.5 -0.5 -0.5 -40 Max 7 VCC + 0.5 VCC + 0.5 +85 +260 Unit V V V C C C KV V -55 +125 2 200 Note: 1. Voltages are measured with respect to ground 2. These are stress ratings only and functional implication is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. DC Electrical Characteristics Unless otherwise stated, 1.2 <= VCC<=5.5V and over the operating temperature range of -40C to +85C. All voltages are referenced to ground. Parameter Supply Voltage ST and PBRST Input High Level ST and PBRST Input High Level ST and PBRST Input Low Level VCC Trip Point (TOL = GND) VCC Trip Point (TOL = VCC) Watchdog Timeout Period Symbol VCC VIH VIH VIL VCCTP VCCTP tTD Conditions Min 1.0 Typ Max 5.5 VCC + 0.3 Unit V V V VCC >=2.7V VCC<2.7V 2 VCC - 0.4V -0.3 2.80 2.47 2.88 2.55 150 0.5 2.97 2.64 250 V V V ms TD = GND 62.5 3.3V P Power Supply Monitor and Reset Circuit Notice: The information in this document is subject to change without notice 5 of 9 February 2005 rev 1.5 Parameter Watchdog Timeout Period Watchdog Timeout Period Output Voltage Output Current Output Current Input Leakage RESET Low Level Internal Pull-up Resistor Operating Current Input Capacitance Output Capacitance PBRST Manual Reset Minimum Low Time Reset Active Time ICC1 CIN COUT tPB tRST Must not exceed tRD miniST Pulse Width VCC Fail Detect to RESET or RESET VCC Slew Rate PBRST Stable LOW to RESET and RESET Active VCC Detect to RESET or RESET inactive VCC Slew Rate Notes ASM1832 Symbol tTD tTD VOH IOH IOL IIL VOL Note 1 Conditions TD = VCC TD Floating I=-500A, VCC < 2.7.V Note 1 Output = 2.4V, VCC >=2.7V Output = 0.4V, VCC >=2.7V Min 500 250 VCC - 0.3V Typ 1200 610 VCC - 0.1V 350 Max 2000 1000 Unit ms ms V A mA 10 -1.0 1.0 0.4 40 20 5 7 A V k A pF pF ms PBRST pin Outputs open, VCC <= 3.6V and all inputs at VCC or GND PBRST = VIL 20 250 610 1000 ms tST mum. Watchdog cannot be disabled. Pulses < 2 s at VCCTP minimum will not cause reset 20 ns tRPD tF tPDLY tRPU tR 5 20 8 s s 20 trise=5s 250 0 610 1000 ms ms ns 1. RESET remains within 0.5V of VCC on power-down until VCC falls below 2V. RESET remains within 0.5V of ground on power-down until VCC falls below 2.0V. 3.3V P Power Supply Monitor and Reset Circuit Notice: The information in this document is subject to change without notice 6 of 9 February 2005 rev 1.5 ASM1832 Package Information MicroSO (8-Pin) Min A A1 A2 b C D e E E1 L S a 0 0.053 0.004 0.049 0.012 0.007 0.032 0.002 0.030 0.004 0.114 0.184 0.114 0.016 Inches Max MicroSO (8-Pin) 0.044 0.006 0.038 0.008 0.122 0.200 0.122 0.026 6 SO (8-Pin) A A1 A2 E H Millimeteres Min 0.81 0.05 0.76 0.30 BSC 0.10 2.90 0.65 BSC 4.67 2.90 0.41 0.52 BSC 0 1.35 0.10 1.25 0.31 0.18 4.90 BSC 3.91 BSC 1.27 BSC 6.00 BSC 0.41 0 0.38 2.92 0.36 1.14 0.20 9.02 7.62 6.10 2.54 BSC 2.92 10.92 3.81 1.27 8 5.33 4.95 0.56 1.78 0.36 10.16 8.26 7.11 8 6 1.75 0.25 1.50 0.51 0.25 5.08 3.10 0.66 0.20 3.10 Max 1.10 0.15 0.97 0.012 BSC 0.0256 BSC 0.0206 BSC SO (8-Pin) 0.069 0.010 0.059 0.020 0.010 B C D E e 0.193 BSC 0.154 BSC 0.050 BSC 0.236 BSC 0.016 0 0.015 0.115 0.014 0.045 0.008 0.355 0.300 0.240 0.115 0.050 Plastic DIP (8-Pin) D A 2 A H C L e B A 1 L A A1 A2 b b2 C D E E1 e eB L D Plastic DIP (8-Pin) 0.210 0.195 0.022 0.070 0.014 0.400 0.325 0.280 0.430 0.150 0.100 BSC 3.3V P Power Supply Monitor and Reset Circuit Notice: The information in this document is subject to change without notice 7 of 9 February 2005 rev 1.5 ASM1832 Ordering Information Part Number Package Operating Temperature Range Maximum Supply Current (A) Voltage Monitoring Application Package Marking TIN - LEAD DEVICES ASM1832 ASM1832S ASM1832U 8-Pin PDIP 8-SO 8-MicroSO -40C to 85C -40C to 85C -40C to 85C 20 20 20 3.3 V 3.3 V 3.3 V ASM1832 ASM1832S ASM1832 LEAD FREE DEVICES ASM1832F ASM1832SF ASM1832UF 8-Pin PDIP 8-SO 8-MicroSO -40C to 85C -40C to 85C -40C to 85C 20 20 20 3.3 V 3.3 V 3.3 V ASM1832F ASM1832SF ASM1832F 3.3V P Power Supply Monitor and Reset Circuit Notice: The information in this document is subject to change without notice 8 of 9 ASM1832 Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Tel: 408 - 855 - 4900 Fax: 408 - 855 - 4999 www.alsc.com Copyright (c) Alliance Semiconductor All Rights Reserved Part Number: ASM1832 Document Version: 1.5 (c) Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. |
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